W83977F-A Datasheet, PDF (66/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
Legacy IR Register:
This is a temporary register that can be accessed and defined by the user.
Advanced IR Register:
Bit 7 MIR, FIR Modes:
FLC_ACT - Flow Control Active
Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that
this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR mode
or MIR/FIR mode operated in DMA function switches to SIR mode.
Bit 6 MIR, FIR Modes:
UNDRN - Underrun
Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO
mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1.
Bit 5 MIR, FIR Modes:
RX_BSY - Receiver Busy
Set to 1 when receiver is busy or active in process.
Remote IR mode:
RX_IP - Receiver in Process
Set to 1 when receiver is in process.
Bit 4: MIR, FIR modes:
LST_FE - Lost Frame End
Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is
read.
Remote IR Modes:
RX_PD - Receiver Pulse Detected
Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is
read.
Bit 3 MIR, FIR Modes:
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure of PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if use in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Bit 2:
Reserved.
Bit 1: MIR, FIR Modes:
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends still stay in receiver FIFO.
Bit 0: MIR, FIR, Remote IR Modes:
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
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