W83977F-A Datasheet, PDF (7/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
12.2.1 Extended Function Registers................................................................................................118
12.2.2 Extended Functions Enable Registers (EFERs) ...................................................................119
12.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers (EFDRs) .119
13. CONFIGURATION REGISTER ..................................................................................................... 120
13.1 Chip (Global) Control Register............................................................................................ 120
13.2 Logical Device 0 (FDC) ....................................................................................................... 125
13.3 Logical Device 1 (Parallel Port)........................................................................................... 128
13.4 Logical Device 2 (UART A)¢).............................................................................................. 130
13.5 Logical Device 3 (UART B) ................................................................................................. 131
13.6 Logical Device 4 (Real Time Clock).................................................................................... 132
13.7 Logical Device 5 (KBC) ....................................................................................................... 133
13.8 Logical Device 6 (IR)........................................................................................................... 134
13.9 Logical Device 7 (Auxiliary I/O Part I) ................................................................................. 136
13.10 Logical Device 8 (Auxiliary I/O Part II) ................................................................................ 139
14. SPECIFICATIONS ......................................................................................................................... 144
14.1 Absolute Maximum Ratings ................................................................................................ 144
14.2 DC CHARACTERISTICS .................................................................................................... 144
14.3 AC Characteristics .............................................................................................................. 148
14.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. ........................................................148
14.3.2 UART/Parallel Port ...............................................................................................................150
14.3.3 Parallel Port Mode Parameters.............................................................................................150
14.3.4 EPP Data or Address Read Cycle Timing Parameters .........................................................151
14.3.5 EPP Data or Address Write Cycle Timing Parameters .........................................................152
14.3.6 Parallel Port FIFO Timing Parameters..................................................................................153
14.3.7 ECP Parallel Port Forward Timing Parameters ....................................................................153
14.3.8 ECP Parallel Port Reverse Timing Parameters ....................................................................153
14.3.9 KBC Timing Parameters.......................................................................................................154
14.3.10 GPIO, ACPI, ROM Interface Timing Parameters..................................................................155
15. TIMING WAVEFORMS.................................................................................................................. 156
15.1 FDC ..................................................................................................................................... 156
15.2 UART/Parallel ..................................................................................................................... 157
15.2.1 Modem Control Timing .........................................................................................................158
15.3 Parallel Port......................................................................................................................... 159
15.3.1 Parallel Port Timing ..............................................................................................................159
15.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) ..........................................................160
15.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)...........................................................161
15.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) ..........................................................162
15.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)...........................................................163
15.3.6 Parallel Port FIFO Timing .....................................................................................................163
15.3.7 ECP Parallel Port Forward Timing........................................................................................164
15.3.8 ECP Parallel Port Reverse Timing........................................................................................164
15.4 KBC ..................................................................................................................................... 165
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