W83977F-A Datasheet, PDF (14/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
4. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O6t - TTL level bi-directional pin with 6 mA source-sink capability
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability
I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-
up resistor
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INc - CMOS level input pin
INcu - CMOS level input pin with internal pull-up resitor
INcs - CMOS level Schmitt-triggered input pin
INts - TTL level Schmitt-triggered input pin
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
4.1 Host Interface
SYMBOL
A0−A10
A11-A14
PIN
74-84
86-89
A15
91
D0−D5
D6−D7
IOR
IOW
AEN
109-114
116-117
105
106
107
IOCHRDY
108
MR
118
I/O
INt
INt
INt
I/O12t
I/O12t
INts
INts
INt
OD24
INts
FUNCTION
System address bus bits 0-10
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
System data bus bits 6-7
CPU I/O read signal
CPU I/O write signal
System address bus enable
In EPP Mode, this pin is the IO Channel Ready output to extend the
host read/write cycle.
Master Reset. Active high. MR is low during normal operations.
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