W83977F-A Datasheet, PDF (76/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
REG.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
SSR
SSR7
SSR6
SSR5
SSR4
SSR3
SSR2
Default Value
1
1
1
0
1
1
BIT 1
SRR1
0
BIT 0
SRR0
0
7.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
REG.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
IRCFG1
-
FSF_TH FEND_M AUX_RX
-
Reset
0
0
0
0
0
Value
BIT 2
-
0
BIT 1
IRHSSL
0
BIT 0
IR_FULL
0
Bit 7:
Bit 6:
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I.
The threshold level values are defined as follows.
FSF_TH
0
1
STATUS FIFO THRESHOLD LEVEL
2
4
Bit 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates as same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
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