W83977F-A Datasheet, PDF (74/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
These are combined to be a 13-bit register. Writing these registers programs the transmitter frame
length of a package. These registers are only valid when APM=1 (automatic package mode,
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame
length if the transmitted data is larger than the programmed frame length. When these registers are
read, they will return the number of bytes which is not transmitted from a frame length programmed.
7.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
REG.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
RFRLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Reset
0
0
0
0
0
0
Value
RFRLH
-
-
-
bit 12
bit 11
bit 10
Reset
-
-
-
0
0
0
Value
BIT 1
bit 1
0
bit 9
0
BIT 0
bit 0
0
bit 8
0
These are combined to be a 13-bit registers and up counter. The length of receiver frame will be
limited to the programmed frame length. If the received frame length is larger than the programmed
receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously,
the receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which
is defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data
bytes of a frame from the receiver.
7.7 Set 5 - Flow control and IR control and Frame Status FIFO registers
ADDRESS
OFFSET
REGISTER
NAME
REGISTER DESCRIPTION
0
FCBLL
Flow Control Baud Rate Divisor Latch Register (Low Byte)
1
FCBHL
Flow Control Baud Rate Divisor Latch Register (High Byte)
2
FC_MD
Flow Control Mode Operation
3
SSR
Sets Select Register
4
IRCFG1
Infrared Configure Register
5
FS_FO
Frame Status FIFO Register
6
RFRLFL Receiver Frame Length FIFO Low Byte
7
RFRLFH Receiver Frame Length FIFO High Byte
7.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
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