W83977F-A Datasheet, PDF (69/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
Bit 1:
Bit 0:
DMA_F - DMA Fairness
DMA_F
Function Description
0
DMA request (DREQ) is forced inactive after 10.5us
1
No effect DMA request.
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
7.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0H. Writing a value selects Register Set.
REG.
SSR
Refault Value
BIT 7
SSR7
1
BIT 6
SSR6
1
BIT 5
SSR5
1
BIT 4
SSR4
0
BIT 3
SSR3
0
BIT 2
SSR2
0
BIT 1
SRR1
0
BIT 0
SRR0
0
7.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)
MODE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Advanced IR DIS_BACK
-
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
Reset Value
0
0
0
0
0
0
0
0
Bit 7:
Bit 6:
Bit 5, 4:
DIS_BACK - Disable Backward Operation
A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR
mode, this bit should be set to 1 to avoid backward operation.
Reserved, write 0.
PR_DIV1~0 - Pre-Divisor 1~0.
These bits select pre-divisor for external input clock 24M Hz. The clock goes through the
pre-divisor then input to baud rate divisor of IR.
PR_DIV1~0
00
01
10
11
PRE-DIVISOR
13.0
1.625
6.5
1
MAX. BAUD RATE
115.2K bps
921.6K bps
230.4K bps
1.5M bps
Bit 3, 2:
RX_FSZ1~0 - Receiver FIFO Size 1~0
These bits setup receiver FIFO size when FIFO is enable.
Publication Release Date: May 2006
-61 -
Revision 0.60