W83977F-A Datasheet, PDF (61/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
Bit 2:
Advanced SIR/ASK-IR modes:
USR_I - IR Status Interrupt.
Set to 1 when overrun error, parity error, stop bit error, or silent byte error detected and
registered in the IR Status Register (USR). Cleared to 0 when USR is read.
MIR, FIR modes:
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been
detected during receiving valid data. Cleared to 0 when this register is read.
Remote Controller Mode: Not used.
Bit 1:
Bit 0:
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold
level; or (2) RBR time-out occurs if the receiver buffer register has valid data and below
the threshold level. Cleared to 0 when RBR is less than threshold level after reading
RBR.
7.2.3.2 IR FIFO Control Register (UFR):
MODE
BIT 7
BIT 6
BIT 5
Legacy IR
Advanced IR
Reset Value
RXFTL1
(MSB)
RXFTL1
(MSB)
0
RXFTL0 (LSB) 0
RXFTL0 (LSB) TXFTL1
(MSB)
0
0
BIT 4
0
TXFTL0
(LSB)
0
BIT 3 BIT 2 BIT 1 BIT 0
0 TXF_RST RXF_RST EN_FIFO
0 TXF_RST RXF_RST EN_FIFO
0
0
0
0
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes and there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
TABLE: FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
Publication Release Date: May 2006
-53 -
Revision 0.60