W83977F-A Datasheet, PDF (62/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be
cleared to logical 0 by itself after being set to logical 1.
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be
cleared to a logical 0 by itself after being set to logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before
other bits of UFR can be programmed.
Advanced IR:
Bit 7, 6: RXFTL1, 0 - Receiver FIFO Threshold Level
Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO
Threshold Level is equal or larger than the defined value shown as follow.
RXFTL1, 0
(BIT 7, 6)
00
01
10
11
RX FIFO THRESHOLD LEVEL
(FIFO SIZE: 16-BYTE)
1
4
8
14
RX FIFO THRESHOLD LEVEL
(FIFO SIZE: 32-BYTE)
1
4
16
26
Bit 5, 4:
Note that the FIFO Size is selectable in SET2.Reg4.
TXFTL1, 0 - Transmitter FIFO Threshold Level
TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter Threshold
Level is less than the programmed value shown as follows.
TXFTL1, 0
(BIT 5, 4)
00
01
10
11
TX FIFO THRESHOLD
LEVEL
(FIFO SIZE: 16-BYTE)
1
3
9
13
Bit 3 ~0 Same as in Legacy IR Mode
TX FIFO THRESHOLD LEVEL
(FIFO SIZE: 32-BYTE)
1
7
17
25
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