W83977F-A Datasheet, PDF (129/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
= 0 Power down
= 1 No Power down
CR23 (Default 0x00)
Bit7-6 : Reserved
Bit 5-3 : APDTMS2 APDTMS1 APDTMS0
= 000 4 seconds count-down time of the APD mode.
= 001 8 seconds count-down time of the APD mode.
= 010 16 seconds count-down time of the APD mode.
= 011 32 seconds count-down time of the APD mode.
= 100 1 minute count-down time of the APD mode.
= 101 2 minutes count-down time of the APD mode.
= 110 4 minutes count-down time of the APD mode.
= 111 16 minutes count-down time of the APD mode.
Bit 2-0 : OSCS2, OSCS1, OSCS0.
= 000 Default power-on state after power on reset.
= 1xx Stop Clock supply to whole chip, but PLL circuit still in operation.
= 001 Stop Clock supply to whole chip and PLL circuit.
= 010 Standby for automatic power-down(APD).
= 011 Automatic power-down(APD) has been happened.
CR24 (Default 0b1ss00sss)
Bit 7 : EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification
Bit 6-5 : CLKSEL, ENPLL
= 00 The clock input on Pin 1 should be 14.31818 Mhz.
= 01 The clock input on Pin 1 should be 24 Mhz.
= 11 The clock input on Pin 1 should be 48 Mhz.
Bit 4 : RWPNPREG
= 0 Disable read/write PnP mode config registers by using the method of non-PnP mode
= 1 Enable read/write PnP mode config registers by using the method of non-PnP mode
Bit 3 : Reserved
Bit 2 : ENKBRTC
= 0 KBC and RTC are disabled after hardware reset.
= 1 KBC and RTC are active after hardware reset.
This bit is read only, and set/reset by hardware setting.
Bit 1 : ENPNP
= 0 Disable Comply PnP
= 1 Enable Comply PnP
Bit 0 : PNPCSV
= 0 The Compatible and Comply PnP has default value
= 1 The Compatible and Comply PnP has no default value
CR25 (Default 0x00)
Bit 7-6 : Reserved
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Publication Release Date: May 2006
Revision 0.60