W83977F-A Datasheet, PDF (77/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register shows the bottom byte of frame status FIFO.
REG.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
FS_FO FSFDR LST_FR
-
MX_LEX PHY_ERR CRC_ERR
Reset
0
0
0
0
0
0
Value
BIT 1
RX_OV
0
BIT 0
FSF_OV
0
Bit 7:
Bit 6:
Bit 5:
FSFDR - Frame Status FIFO Data Ready
Indicate that a data byte is valid in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Reserved.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when incoming data exceeds programmed maximum frame length defined in
Set4.Reg6 and Set4.Reg7. This bit is in frame status FIFO bottom and is valid only when
FSFDR=1 (Frame Status FIFO Data Ready).
PHY_ERR - Physical Error
When receiving data, any physical layer error as defined in IrDA 1.1 will set this bit to 1.
This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO
Data Ready).
CRC_ERR - CRC Error
Set to 1 when receive a bad CRC in a frame. This CRC belongs to physical layer as defined
in IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame
Status FIFO Data Ready).
RX_OV - Received Data Overrun
Set to 1 when receiver FIFO overruns.
FSF_OV - Frame Status FIFO Overrun
Set to 1 When frame status FIFO overruns.
7.7.6
Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame
Number (LST_NU)
REG.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RFLFL/ LST_NU
Reset Value
RFLFH
Reset Value
Bit 7
0
-
0
Bit 6
0
-
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
-
Bit 12
Bit 11
Bit 10
Bit 9
0
0
0
0
0
Bit 0
0
Bit 8
0
Publication Release Date: May 2006
-69 -
Revision 0.60