W83977F-A Datasheet, PDF (48/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
TABLE 6-1 UART Register Bit Map
BIT NUMBER
REGISTER
ADDRESS BASE
0
1
2
3
4
5
6
7
+0
BDLAB =
0
Receiver
Buffer
Register
(Read Only)
RBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data RX Data RX Data
Bit 5
Bit 6
Bit 7
+0
BDLAB =
0
Transmitter
Buffer
Register
(Write Only)
TBR
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
+1
Interrupt ICR RBR Data TBR
USR
HSR
0
0
0
0
BDLAB =
0
Control
Register
Ready
Interrupt
Enable
(ERDRI)
Empty
Interrupt
Enable
(ETBREI)
Interrupt
Enable
(EUSRI)
Interrupt
Enable
(EHSRI)
+2
Interrupt ISR "0" if Interrupt Interrupt Interrupt
0
Status
Interrupt Status Status Status
Register
(Read Only)
Pending _{Bit (0)}
Bit (1) Bit (2)**
0
FIFOs FIFOs
Enabled Enabled
**
**
+ 2 UART FIFO UFR FIFO
RCVR
XMIT
DMA Reserved Reversed RX
RX
Control
Enable FIFO
FIFO
Mode
Interrupt Interrupt
Register
Reset
Reset
Select
Active Active
(Write Only)
Level
Level
(LSB) (MSB)
+3
UART UCR Data
Data Multiple Parity
Even
Parity
Set Baudrate
Control
Length Length Stop Bits
Bit
Parity Bit Fixed Silence Divisor
Register
Select Select Enable Enable Enable Enable Enable Latch
Bit 0
(DLS0)
Bit 1
(MSBE)
(DLS1)
(PBE)
(EPE)
PBFE)
(SSE) ^{Access Bit}
(BDLAB)
+4
Handshake HCR Data Request Loopback IRQ
Internal
0
0
0
Control
Terminal
to
RI
Enable Loopback
Register
Ready
Send
Input
Enable
(DTR) (RTS)
+ 5 UART Status USR RBR Data Overrun Parity Bit No Stop Silent
TBR
TSR RX FIFO
Register
Ready
Error
Error
Bit
Byte
Empty Empty
Error
(RDR)
(OER)
(PBER)
Error Detected _{(TBRE) (TSRE)} Indication
(NSER) (SBD)
(RFEI) **
+ 6 Handshake HSR CTS
DSR RI Falling DCD
Clear Data Set Ring
Data
Status
Toggling Toggling Edge Toggling to Send Ready Indicator Carrier
Register
(TCTS) (TDSR) (FERI) (TDCD) (CTS) (DSR)
(RI)
Detect
(DCD)
+ 7 User Defined UDR Bit 0
Register
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+0
Baudrate BLL
BDLAB = ^{Divisor Latch}
1
Low
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+1
Baudrate BHL
BDLAB = ^{Divisor Latch}
1
High
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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