W83977F-A Datasheet, PDF (5/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number
(LST_NU) .............................................................................................................................................69
7.8 Set6 - IR Physical Layer Control Registers .......................................................................... 70
7.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)...........................................................70
7.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width..............................................................71
7.8.3 Set6.Reg2 - SIR Pulse Width .................................................................................................72
7.8.4 Set6.Reg3 - Set Select Register.............................................................................................72
7.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) .................................72
7.9 Set7 - Remote control and IR module selection registers .................................................... 73
7.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) ...................................................73
7.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) ...............................................75
7.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG) .....................................................76
7.9.4 Set7.Reg3 - Sets Select Register (SSR) ................................................................................77
7.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) ...............................................77
7.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) ...............................................78
7.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) ...............................................78
7.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR).......................................................79
8. PARALLEL PORT ............................................................................................................................ 81
8.1 Printer Interface Logic ........................................................................................................... 81
8.2 Enhanced Parallel Port (EPP)............................................................................................... 82
8.2.1 Data Swapper.........................................................................................................................82
8.2.2 Printer Status Buffer ...............................................................................................................83
8.2.3 Printer Control Latch and Printer Control Swapper.................................................................84
8.2.4 EPP Address Port...................................................................................................................84
8.2.5 EPP Data Port 0-3 ..................................................................................................................85
8.2.6 Bit Map of Parallel Port and EPP Registers............................................................................85
8.2.7 EPP Pin Descriptions .............................................................................................................86
8.2.8 EPP Operation .......................................................................................................................86
8.3 Extended Capabilities Parallel (ECP) Port............................................................................ 87
8.3.1 ECP Register and Mode Definitions .......................................................................................87
8.3.2 Data and ecpAFifo Port ..........................................................................................................88
8.3.3 Device Status Register (DSR) ................................................................................................88
8.3.4 Device Control Register (DCR)...............................................................................................89
8.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ...........................................................................89
8.3.6 ecpDFifo (ECP Data FIFO) Mode = 011.................................................................................90
8.3.7 tFifo (Test FIFO Mode) Mode = 110 .......................................................................................90
8.3.8 cnfgA (Configuration Register A) Mode = 111 ........................................................................90
8.3.9 cnfgB (Configuration Register B) Mode = 111 ........................................................................90
8.3.10 ecr (Extended Control Register) Mode = all............................................................................91
8.3.11 Bit Map of ECP Port Registers ...............................................................................................92
8.3.12 ECP Pin Descriptions .............................................................................................................93
8.3.13 ECP Operation .......................................................................................................................93
8.3.14 FIFO Operation ......................................................................................................................94
8.3.15 DMA Transfers .......................................................................................................................94
8.3.16 Programmed I/O (NON-DMA) Mode.......................................................................................94
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