W83977F-A Datasheet, PDF (108/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
PERIODIC INTERRUPT RATE TABLE
RS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TIME BASE
None
3.90625mS / 256Hz
7.8125mS / 128Hz
122.070μS / 8.192KHz
244.141μS / 4.096KHz
488.281μS / 2.048KHz
976.562μS / 1.024KHz
1.953125mS / 512Hz
3.90625mS / 256Hz
7.8125mS / 128Hz
15.625ms / 64Hz
31.25ms / 32Hz
62.5ms / 16Hz
125ms / 8Hz
250ms / 4Hz
500ms / 2Hz
9.3.2 Register 0Bh (Read/Write)
BIT
7
6
5
4
3
2
1
0
NAME
SET
PE
AE
UE Reserved DM
12/24
DSE
SET
When the SET bit is set, any occurring update cycle is aborted and registers (Register 00h~09h,
Register (40h~48h) may be modified without entering an update cycle. When this bit is cleared, the
update cycle function occurs once per second. This bit is not affected by any other internal functions
or by a RESET.
PE
A "1" on the periodic interrupt enable bit enables the periodic interrupt flag (PF) bit in Register 0Ch to
assert an interrupt.
A "0" on this bit blocks the IRQ output from being driven by a periodic interrupt. This bit can not be
modified by any internal function, but it may be cleared by a RESET.
AE
A "1" on the enable bit of alarm A enables the alarm A flag (AF) bit in Register 0Ch to assert an
interrupt.
A "0" on this bit prohibits alarm A interrupt. The RESET signal clears AE to "0". This bit can not be
modified by any internal function.
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