W83977F-A Datasheet, PDF (65/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.2.6 Set0.Reg5 - IR Status Register (USR)
MODE
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR
Advanced IR
Reset Value
RFEI
LB_INFR
0
TSRE
TSRE
0
TBRE
TBRE
0
SBD
MX_LEX
0
NSER
PBER
PHY_ERR CRC_ERR
0
0
OER
OER
0
RDR
RDR
0
Legacy IR Register: These registers are defined the same as previous description.
Advanced IR Register:
Bit 7: MIR, FIR Modes:
LB_INFR - Last Byte In Frame End
Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame
from another when RX FIFO has more than one frame.
Bit 6, 5: Same as legacy IR description.
Bit 4: MIR, FIR modes:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when the length of a frame from the receiver has exceeded the programmed
frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not
receive any data to RX FIFO.
Bit 3: MIR, FIR modes:
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in
physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will be
aborted and a frame end signal is set to 1.
Bit 2: MIR, FIR Modes:
CRC_ERR - CRC Error
Set to 1 when an attached CRC is erroneous.
Bit 1, 0: OER - Overrun Error, RDR - RBR Data Ready
Definitions are the same as legacy IR.
7.2.7 Set0.Reg6 - Reserved
7.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)
MODE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Legacy IR Bit 7
Advanced FLC_ACT
IR
Reset
0
Value
Bit 6
UNDRN
0
Bit 5
RX_BSY/
RX_IP
0
Bit 4
LST_FE/
RX_PD
0
Bit 3
S_FEND
0
BIT 2
Bit 2
0
0
BIT 1
Bit 1
LB_SF
BIT 0
Bit 0
RX_TO
0
0
Publication Release Date: May 2006
-57 -
Revision 0.60