W83791G Datasheet, PDF (63/99 Pages) Winbond – Winbond H/W Monitoring IC

W83791D/G
7.70 FAN 3 Pre-Scale Register ⎯ Index 93h (Bank 0)
Power on default: 01h
BIT
NAME
ATTRIBUTE
DESCRIPTION
7 PWM_CLK_SEL3
R/W
PWM 3 Input Clock Select. This bit select Fan 3 input
clock to pre-scale divider.
0: 3 MHz
1: 125 KHz
6-0 PRE_SCALE3[6:0]
R/W
Fan 3 Input Clock Pre-Scale. The divider of input
clock is the number defined by pre-scale. Thus, writing
0 transfers the input clock directly to counter. The
maximum divider is 128 (7Fh).
00h : divider is 1
01h : divider is 2
02h : divider is 3
:
:
PWM frequency = (Input clock / pre-scale) / 256
7.71 FAN 3 Duty Cycle Select Register ⎯ Index 94h (Bank 0)
Power on default: FFh
BIT
NAME
ATTRIBUTE
DESCRIPTION
7-0 F3_DC[7:0]
R/W
Fan 3 Duty Cycle. This 8-bit register determines the
number of input clock cycles, out of 256-cycle period, during
which the PWM output is high. During smart fan3 control
mode, read this register would return smart fan duty cycle.
00h: PWM output is always logical Low.
FFh: PWM output is always logical High.
XXh: PWM output logical High percentage is
(XX/256*100%) during one cycle.
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Publication Release Date: April 14, 2006
Revision 1.1