W83791G Datasheet, PDF (47/99 Pages) Winbond – Winbond H/W Monitoring IC

W83791D/G
7.29 IRQ Mask Register 1 ⎯ Index 45h (Bank 0)
Power on default: 00h
BIT NAME
7 FAN2
6 FAN1
5 TEMP2
4 TEMP1
3 5VDD
2 +3.3VIN
1 VINR0
0 Vcore
ATTRIBUTE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
A one disables the corresponding interrupt status bit for IRQ
interrupt.
7.30 IRQ Mask Register 2 ⎯ Index 46h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE
DESCRIPTION
7 Chassis
clear
R/W
A one outputs a minimum 20 ms active low pulse on the Case
Open pin. The register bit self clears after the pulse has been
output.
6 VINR1
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
5 TEMP3
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
4 Chassis
Intrusion
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
3 FAN3
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
2 -5VIN
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
1 -12VIN
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
0 +12VIN
R/W
A one disables the corresponding interrupt status bit for IRQ
interrupt.
Note: IRQ mask register III is defined at index 9Dh
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Publication Release Date: April 14, 2006
Revision 1.1