W83791G Datasheet, PDF (46/99 Pages) Winbond – Winbond H/W Monitoring IC

W83791D/G
7.27 SMI# Mask Register 1 ⎯ Index 43h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE
DESCRIPTION
7 FAN2
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt
6 FAN1
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
5 TEMP2
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
4 TEMP1
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
3 5VDD
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
2 +3.3VIN
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
1 VINR0
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
0 Vcore
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
7.28 SMI# Mask Register 2 ⎯ Index 44h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE
DESCRIPTION
7 Reserved
Reserved
6 VINR1
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
5 TEMP3
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
4 Chassis
Intrusion
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
3 FAN3
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
2 -5VIN
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
1 -12VIN
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
0 +12VIN
R/W
A one disables the corresponding interrupt status bit for SMI#
interrupt.
Note: SMI# Mask register III is defined at index 9Ch
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Publication Release Date: April 14, 2006
Revision 1.1