W83793G Datasheet, PDF (50/131 Pages) Winbond – Winbond H/W Monitor

W83793G
VOLTAGE READOUT
BIT
7
6
5
4
3
2
1
0
Name
Voltage Voltage
VIN LOW BIT READOUT
BIT
7
6
5
4
3
2
1
0
Name
Reserve
VttL
VCOREBL
VcoreAL
Channel VcoreA/B, and Vtt combined two registers for each channel to express their monitor result,
and so it is 10-bit format data. For example, Monitored value of VCOREA can get from combination of
VCOREA Readout and VIN Low bit Readout bit1~0. In order to read the correct monitor result, it
needs to read high byte first than to read its corresponding low byte. The real voltage calculation of
these three channels should follow the formula
Vcore AVoltage = (CR [10]*4 + CR [1B] &0x03) * 0.002;
Vcore BVoltage = (CR [11]*4 + (CR [1B] &0x0C)/4) * 0.002;
Vtt
Voltage = (CR [12]*4 + (CR [1B] &0x30)/16) * 0.002;
The rest of voltage channels only supply 8-bit output format. The real voltage calculation of these
three channels should follow the formula
VSEN1
Voltage = CR [14] * (2 * 0.008);
VSEN2
Voltage = CR [15] * (2 * 0.008);
3VSEN
Voltage = CR [16] * (2 * 0.008);
12VSEN
Voltage = CR [17] * 0.008;
5VDD Voltage = CR [18] * (2 * 1.5 * 0.008)+0.15;
5VSB Voltage = CR [19] * (2 * 1.5 * 0.008)+0.15;
VBAT Voltage = CR [1A] * (2 * 0.008);
8.9.2.2 Voltage Channel Limitation Registers
Location :
VCOREA High Limit Bank 0 Address 60_HEX
VCOREA Low Limit Bank 0 Address 61_HEX
VCOREB High Limit Bank 0 Address 62_HEX
VCOREB Low Limit Bank 0 Address 63_HEX
Vtt High Limit
Bank 0 Address 64_HEX
Vtt Low Limit
Bank 0 Address 65_HEX
High Limit Low bit
Bank 0 Address 68_HEX
Low Limit Low bit
Bank 0 Address 69_HEX
VSEN1 High Limit
Bank 0 Address 6A_HEX
VSEN1 Low Limit
Bank 0 Address 6B_HEX
VSEN2 High Limit
Bank 0 Address 6C_HEX
VSEN2 Low Limi Bank 0 Address 6D_HEX
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