W83793G Datasheet, PDF (43/131 Pages) Winbond – Winbond H/W Monitor

W83793G
Continued.
BIT
DESCRIPTION
EN_FANIN11.(Fan In 11 Enable Bit)
5
If SID_SEL = 10, Setting to 1 will enable FANIN11 monitor.
If cleared, Pin39 can be selected as Processor A VID Bit 2(EN_D-VID).
EN_FANIN10.(Fan In 10 Enable Bit)
4
If SIC_SEL = 10, Setting to 1 will enable FANIN10 monitor.
If cleared, Pin 38 can be selected as Processor A VID Bit 1.
EN_FANIN9.(Fan In 9 Enable Bit)
3
If SIC_SEL = 10, Setting to 1 will enable FANIN9 monitor.
If cleared, Pin 37 can be selected as Processor A VID Bit 0(EN_D-VID).
EN_FANIN8.(Fan In 8 Enable Bit)
Setting to 1 enables FANIN8 monitor.
2
If FANIN8 connect to Pin55 is desired, setting VIDBSEL = 0, SIDB_SEL = 0 and
FAN8SEL = 0 are must.
If FANIN8 connect to Pin 10, Setting FAN8SEL = 1 is a must.
Setting to 0 enables Pin 10 with Processor A VID Bit 4(EN_D-VID)
EN_FANIN7.(Fan In 7 Enable Bit)
1
If VIDBSEL = 0, Setting to 1 will enable FANIN7 monitor.
Setting to 0 enables Pin 53 with Processor B VID Bit 4(VIDBSEL = 1)
EN_FANIN6.(Fan In 6 Enable Bit)
0
If VIDBSEL = 0, Setting to 1 will enable FANIN6 monitor.
Setting to 0 enables Pin 51 with Processor B VID Bit2(VIDBSEL = 1)
8.7.2.3 FANIN Input Pin Redirection Register(FANIN_Sel)
Location :
Type :
Bank 0 Address 5D_HEX
Read / Write
Reset :
VSB5V(Pin 7) Rising,
Init Reset(CR40.Bit7) is set,
VDD5V(Pin 25) Rising @ RST_VDD_MD(CR40.Bit4) set,
SYSRSTIN_N(Pin 15) Falling @ SYSRST_MD(CR40.Bit5) set.
BIT
7
Name
Reset 0
6
5
Reserved
0
0
FANIN_SEL
4
3
2
1
0
FANIN12Sel FANIN11Sel FANIN10Sel FANIN9Sel
0
0
0
0
0
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Publication Release Date: Dec. 11, 2006
Revision 1.0