W83793G Datasheet, PDF (24/131 Pages) Winbond – Winbond H/W Monitor

W83793G
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BIT
DESCRIPTION
EN_BAT_MNT.
3
Write 1, enable battery voltage monitor. Write 0, disable battery voltage monitor. If enable
this bit, the monitor value is valid after one monitor cycle.
EN_WDT.
2
Set this bit to 1 will enable the Watch Dog Timer function. Watch dog timer function will
reset system (pin 47) while it timeouts.
INT_Clear.
1
A one disables the SMI# and IRQ# outputs without affecting the contents of Interrupt
Status Registers. The device will stop monitoring at last channel. It will resume upon clearing
of this bit.
START.
0
1 : enables startup of monitoring operations;
0 : puts the analog part in Power-down mode.
8.4 VID Control/Status Registers
W83793G provides dual Vcore monitoring channels. Vcore Channels are automatically monitored
once 5VSB applied onto W83793G, but W83793G will issue alert information only when their
corresponding high/low limit is being violated. ASF is also based on these limit register to judge the
current channel status and report to host.
Two methods are used to assign the Vcore Limits. Assigning it manually; or assigning it automatically
by VID inputs. The following registers set can let users choose their preferred method.
8.4.1 VID Control/Status Registers Map
MNEMONIC
REGISTER NAME
TYPE
VIDIN_A
VIDA Input Value
RO
VIDIN_B
VIDB Input Value
RO
VIDA_Latch
VIDA Latch Value
RO
VIDB_Latch
VIDB Latch Value
RO
VID_Control
VID Control
R/W
VCORE_LIMHI
Vcore High Tolerance
R/W
VCORE_LIMLO
Vcore Low Tolerance
R/W
W83793G supplies two sets of VID input pin for VOCREA and VCOREB channels. If dynamic VID
function is enabled, the high/low limit of VCOREA and VCOREB channel will auto-update while VID
input value change.
Some VIDA and all VIDB input pins are multi function pin. It needs programming Bank0 CR58 Multi
function Pin Control Registers adequately.
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