W83793G Datasheet, PDF (23/131 Pages) Winbond – Winbond H/W Monitor

W83793G
Continued.
BIT
DESCRIPTION
I2CADDR75A.
The value of I2CADDR75B is trapping PADDR0 (pin42) and PADDR1 (pin44) at 100ms
after VSB power good issue.
ADDR1 ADDR0 I2CADDR75A Temperature sensor 1 I2C
2-0
0
0
000
0
1
001
1
0
010
1
1
011
Address
90_HEX
92_HEX
94_HEX
96_HEX
8.3.2.3 Configuration Register
Location:
Type:
Bank 0 Address 40_HEX
Read / Write
Reset:
bit 0~3 & 7:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
Bit 4 & 5:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
CONFIG
BIT 7
6
5
4
3
2
1
0
Name INIT Reserve SYSRST_MD RST_VDD_MD EN_BAT_MNT EN_WDT INT_Clear START
Reset 0
0
0
0
0
0
0
0
BIT
DESCRIPTION
INIT.
7
Set one restores power on default value to all registers except the Serial Bus Address
register. This bit clears itself since the power on default is zero.
6 Reserved
SYSRST_MD.
5
Write 1, whole chip will reset when SYSRSTIN# input. Write 0, no any operation when
SYSRSTIN# input.
RST_VDD_MD.
4
Write 1, whole chip will reset when 5VDD up. Write 0, no any operation when 5VDD up.
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Publication Release Date: Dec. 11, 2006
Revision 1.0