W83793G Datasheet, PDF (32/131 Pages) Winbond – Winbond H/W Monitor

W83793G
BIT
Name
Reset
7
12VSEN
0
6
3VSEN
0
INT_STS1
5
4
3
2
VSEN2 VSEN1 Reserve VTT
0
0
0
0
BIT
7
6
5
Name TD4
TD3
TD2
Reset 0
0
0
INT_STS2
4
3
TD1
VIDCHG
0
0
2
VBAT
0
1
VCOREB
0
0
VCOREA
0
1
5VSB
0
0
5VDD
0
INT_STS3
BIT
7
6
5
4
3
2
1
0
Name FANIN6 FANIN5 FANIN4 FANIN3 FANIN2 FANIN1 TR2
TR1
Reset
0
0
0
0
0
0
0
0
BIT
Name
Reset
7
Reserve
0
6
Chassis
0
INT_STS4
5
4
3
FANIN12 FANIN11 FANIN10
0
0
0
2
FANIN9
0
1
FANIN8
0
0
FANIN7
0
BIT
Name
Reset
7
6
Reserve
0
0
5
TART6
0
INT_STS5
4
3
TART5 TART4
0
0
2
TART3
0
1
TART2
0
0
TART1
0
8.5.2.2 SMI/IRM Mask Register (MASK)
Set to one will disable the corresponding interrupt sources. Clear to 0 will enable that interrupt
source.
SMI Mask4 bit 7 is CLR_CHS (Clear Chassis), write this bit with an one will clear internal caseopen
latch, and after latch is clear, CLR_CHS will be reset to 0 itself.
Location:
MASK1 - Bank 0 Address 46_HEX
MASK2 - Bank 0 Address 47_HEX
MASK3 - Bank 0 Address 48_HEX
MASK4 - Bank 0 Address 49_HEX
MASK5 - Bank 0 Address 4A_HEX
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