W29N02GVSIAA Datasheet, PDF (44/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9.4.2 TWO PLANE BLOCK ERASE
TWO PLANE BLOCK ERASE (60h-D1h) command indicates two blocks in the specified plane that is
to be erased. To start ERASE operation for indicated blocks in the specified plane, write the BLOCK
ERASE (60h-D0h) command.
To indicate a block to be erased, writing 60h to the command register, then, write three address cycles
containing the row address, the page address is ignored. By writing D1h command to command
register, the device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To confirm busy status during tDBSY, the host can monitor RY/#BY signal. Instead, system can use
READ STATUS (70h) or READ STATUS ENHANCED (78h) commands. When the status shows
ready (SR BIT 6 = 1, SR BIT 5 = 1), additional TWO PLANE BLOCK ERASE commands can be
issued for erasing two blocks in a specified plane.
When system issues TWO PLANE BLOCK ERASE (60h-D1h), and BLOCK ERASE (60h-D0h)
commands, READ STATUS (70h) command can confirm whether the operation(s) passed or failed.
If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1), READ STATUS
ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE BLOCK ERASE commands require three cycles of row addresses; one address
indicates the operational plane. These addresses are subject to the following requirements:
• The plane select bit, A18, must be different for each issued address.
• Block address (A28-A19) of first input is don’t care. It follows secondary inputted block address.
Two plane operations must be same type operation across the planes; for example, it is not possible
to perform a PROGRAM operation on one plane with an ERASE operation on another.
CLE
#CE
#WE
ALE
#RE
I/Ox
RY/#BY
60h R1A R2A R3A D1h
tDBSY
Busy
60h R1B R2B R3B D0h
tBERS
Busy
Figure 9-24 Two Plane Block Erase Operation
Don’t care
Release Date: February 1^st, 2016
44
– Revision B