W29N02GVSIAA Datasheet, PDF (32/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9.2 PROGRAM operation
9.2.1 PAGE PROGRAM (80h-10h)
The W29N02GV Page Program command will program pages sequentially within a block, from the
lower order page address to higher order page address. Programming pages out of sequence is
prohibited. The W29N02GV supports partial-page programming operations up to 4 times before an
erase is required if partitioning a page. Note; programming a single bit more than once without first
erasing it is not supported.
9.2.2 SERIAL DATA INPUT (80h)
Page Program operation starts with the execution of the Serial Data Input command (80h) to the
Command Register, following next by inputting five address cycles and then the data is loaded. Serial
data is loaded to Cache Register with each #WE cycle. The Program command (10h) is written to the
Command Register after the serial data input is finished. At this time the internal write state controller
automatically executes the algorithms for program and verifies operations. Once the programming
starts, determining the completion of the program process can be done by monitoring the RY/#BY
output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during
the internal array programming operation during the period of (tPROG). During page program
operation, only two commands are available, READ STATUS (70h) and RESET (FFh). When the
device status goes to the ready state, Status Register Bit 0 (I/O0) indicates whether the program
operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-13). The Command Register remains in
read status mode until the next command is issued.
RY/#BY
tPROG
I/Ox
80h
Address (5cycles)
Din
10h
70h
Status
I/O0=0pass
I/O0=1fail
Figure 9-12 Page Program
Release Date: February 1^st, 2016
32
– Revision B