W29N02GVSIAA Datasheet, PDF (35/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9.2.5 TWO PLANE PAGE PROGRAM
TWO PLANE PAGE PROGRAM command make it possible for host to input data to the addressed
plane's cache register and queue the cache register to be moved to the NAND Flash array.
This command can be issued several times. Each time a new plane address is specified that plane
is also queued for data transfer. To input data for the final plane and to begin the program operation
for all previously queued planes, either the PAGE PROGRAM command or the CACHE PROGRAM
command have to be issued. All of the queued planes will move the data to the NAND Flash array.
when it is ready (SR BIT 6 = 1),this command is accepted.
At the block and page address is specified, input a page to the cache register and queue it to be
moved to the NAND Flash array ,the 80h is issued to the command register. Unless this command
has been preceded by a TWO PLANE PAGE PROGRAM command, issuing the 80h to the command
register clears all of the cache registers' contents on the selected target. Write five address cycles
containing the column address and row address; data input cycles follow. Serial data is input
beginning at the column address specified. At any time, while the data input cycle, the RANDOM
DATA INPUT (85h) command can be issued. When data input is complete, write 11h to the command
register. The device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To ascertain the progress of tDBSY, the host can monitor the target's RY/#BY signal or, the status
operations (70h, 78h) can be used alternatively,. When the device status shows that it is ready (SR
BIT 6 = 1), additional TWO PLANE PAGE PROGRAM commands can be issued to queue additional
planes for data transfer, then, the PAGE PROGRAM or CACHE PROGRAM commands can be
issued.
When the PAGE PROGRAM command is used as the final command of a two plane program
operation, data is transferred from the cache registers to the NAND Flash array for all of the
addressed planes during tPROG. When the device is ready (SR BIT 6 = 1, SR BIT 5 = 1), the host
should check the status of the SR BIT 0 for each of the planes to verify that programming completed
successfully.
When the CACHE PROGRAM command is used as the final command of a program cache two plane
operation, data is transferred from the cache registers to the data registers after the previous array
operations completed. Then,The data is moved from the data registers to the NAND Flash array for
all of the addressed planes. This occurs while tCBSY. After tCBSY, the host should check the status
of the SR BIT 1 for each of the planes from the previous program cache operation, if any, to verify
that programming completed successfully.
When system issues TWO PLANE PAGE PROGRAM, PAGE PROGRAM, and CACHE PROGRAM
commands, READ STATUS (70h) command can confirm whether the operation(s) passed or failed.
If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1 and/or SR BIT 1
= 1), READ STATUS ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE PROGRAM commands require five-cycle addresses, one address indicates the
operational plane. These addresses are subject to the following requirements:
• The column address bits must be valid address for each plane
• The plane select bit, A18, must be set to “L” for 1^st address input, and set to “H” for 2^nd address input.
• The page address (A17-A12) and block address (A28-A19) of first input are don’t care. It follows
secondary inputted page address and block address.
Two plane operations must be same type operation across the planes; for example, it is not possible
to perform a PROGRAM operation on one plane with an ERASE operation on another.
Release Date: February 1^st, 2016
35
– Revision B