W29N02GVSIAA Datasheet, PDF (29/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
#CE
CLE
#WE
#RE
I/Ox
tCLR
tREA
70h
Status Output
Figure 9-9 Read Status Operation
SR bit
Page Read
Cache Read Page Program
Cache
Program
Block Erase
Definition
I/O 0
Not Use
Not Use
Pass/Fail
Pass/Fail(N)
Pass/Fail
0=Successful
Program/Erase
1=Error
in Program/Erase
I/O 1
Not Use
Not Use
Not Use
Pass/Fail(N-1)
Not Use
0=Successful
Program
1=Error in Program
I/O 2
Not Use
Not Use
Not Use
Not Use
Not Use 0
I/O 3
Not Use
Not Use
Not Use
Not Use
Not Use 0
I/O 4
Not Use
Not Use
Not Use
Not Use
Not Use 0
I/O 5
Ready/Busy Ready/Busy1
Ready/Busy
Ready/Busy
Ready = 1
Ready/Busy
Busy = 0
I/O 6
Cache
Ready/Busy
Ready/Busy2
Ready/Busy
Cache
Ready/Busy
Ready = 1
Ready/Busy
Busy = 0
Unprotected = 1
I/O 7 Write Protect Write Protect Write Protect Write Protect Write Protect
Protected = 0
Table 9-4 Status Register Bit Definition
Notes:
1. SR bit 5 is 0 during the actual programming operation. If cache mode is used, this bit will be 1 when all
internal operations are complete.
2. SR bit 6 is 1 when the Cache Register is ready to accept new data. RY/#BY follows bit 6.
Release Date: February 1^st, 2016
29
– Revision B