W29N02GVSIAA Datasheet, PDF (37/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
CLE
#CE
#WE
ALE
#RE
I/O×
RY/#BY
tWC
tADL
tWHBL
80h
Address (5cycles)
A0 – A11 = Valid
A12 – A17 = don’t care
A18 = ‘Low’
A19 – A28 = don’t care
Din
N
Din
M
11h
※
81h
tDBSY
※81h: Traditional Protocol 80h:ONFI Protocol
tADL
tADL
Address (5cycles)
A0 – A11 = Valid
A12 – A17 = Valid
A18 = set to ’High’
A19 – A28 = Valid
Din Din
NM
15h
tCBSY
Return to A Can be repeated up
to 63times
A
CLE
#CE
tADL
#WE
ALE
#RE
I/O×
RY/#BY
A
80h
Address (5cycles)
Din
N
Din
M
11h
A0 – A11 = Valid
A12 – A17 = don’t care
A18 = ‘Low’
A19 – A28 = don’t care
※
81h
tDBSY
1.In this figure the Read Status Register (70h) is used ,but the Read Status Enhanced (78h) can be used as well.
Address (5cycles)
A0 – A11 = Valid
A12 – A17 = Valid
A18 = set to ’High’
A19 – A28 = Valid
10h ^{Din Din}
NM
70h SR0
tPROG
Figure 9-17 Two Plane Cache Program
Release Date: February 1^st, 2016
37
– Revision B