W29N02GVSIAA Datasheet, PDF (18/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
Cache Register data is available and can be read out of the Cache Register by with toggling #RE,
which starts at address column 0. If it is desired to start at a different column address, a RANDOM
DATA OUTPUT (05h-E0h) command can be used to change the column address to read out the data.
At this point in the procedure when completing the read of the desired number of bytes, one of two
things can be chosen. Continue CACHE READ (31h or 00h-31h) operations or end the CACHE READ
mode with a LAST ADDRESS CACHE READ (3Fh) command.
To continue with the read operations, execute the CACHE READ (31h or 00h-31h) command. The
RY/#BY signal goes LOW for the period of tRCBSY while data is copied from Data Register to the
Cache Register and the next page of data starts being copied from the NAND array to the Data
Register. When RY/#BY signal goes HIGH signifying that the Cache Register data is available, at this
time #RE can start toggling to output the desired data starting at column 0 address or using the
RANDOM DATA OUPUT command for random column address access.
To terminate the CACHE READ operations a LAST ADDRESS CACHE READ (3Fh) command is
issued, RY/#BY signal goes LOW and the Data Register contents is copied to the Cache Register.
At the completion of the Data Register to Cache Register transfer, RY/#BY goes HIGH indicating data
is available at the output of the Cache Register. At this point Data can be read by toggling #RE starting
at column address 0 or using the RANDOM DATA OUPUT command for random column address
access. The device NAND array is ready for next command set.
Release Date: February 1^st, 2016
18
– Revision B