W29N02GVSIAA Datasheet, PDF (43/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9.4 BLOCK ERASE operation
9.4.1 BLOCK ERASE (60h-D0h)
Erase operations happen at the architectural block unit. This W29N02GV has 2048 erase blocks.
Each block is organized into 64 pages (x8:2112 bytes/page, x16:1056 words/page), 132K bytes
(x8:128K + 4K bytes, x16:64 K+ 2Kwords)/block. The BLOCK ERASE command operates on a block
by block basis.
Erase Setup command (60h) is written to the Command Register. Next, the three cycle block address
is written to the device. The page address bits are loaded during address block address cycle, but
are ignored. The Erase Confirm command (D0h) is written to the Command Register at the rising
edge of #WE, RY/#BY goes LOW and the internal controller automatically handles the block erase
sequence of operation. RY/#BY goes LOW during Block Erase internal operations for a period of
tBERS,
The READ STATUS (70h) command can be used for confirm block erase status. When Status
Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0) will
indicate a pass/fail condition (see Figure 9-24).
CLE
#CE
#WE
ALE
#RE
I/Ox
60h
Address Input (3cycles)
D0h
RY/#BY
tBERS
70h
Status Output
I/ O 0 = 0 pass
I/ O 0 = 1 fail
Figure 9-23 Block Erase Operation
Don’t care
Release Date: February 1^st, 2016
43
– Revision B