W29N02GVSIAA Datasheet, PDF (13/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
6. MEMORY ARRAY ORGANIZATION
6.1 Array Organization (x8)
2112 bytes
2112 bytes
Cache Register
Data Register
1024
blocks
Per plane
2048
blocks
Per device
2048 64
2048
64
2048
64
2048
64
1 block
1 block
Plane of even
numbered b^-locks
nuPmlabneeroefd^{- obdldocks}
DQ7
DQ0
1page = (2k+64bytes)
1block = (2k+64）bytes×64 pages
= (128k+4k)byte
1plane = (128k+4k)byte×1024blocks
= 1056Mb
1device = 1056M ×2planes
= 2112Mb
Figure 6-1 Array Organization
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1^st cycle
A7
A6
A5
A4
A3
A2
A1
A0
2^nd cycle
L
L
L
L
A11
A10
A9
A8
3^rd cycle A19
A18
A17
A16
A15
A14
A13
A12
4^th cycle A27
A26
A25
A24
A23
A22
A21
A20
5^th cycle
L
L
L
L
L
L
L
A28
Table 6-1 Addressing
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A28 during the 3rd, 4th and 5th cycles
are row addresses.
3. A18 is plane address
4. The device ignores any additional address inputs that exceed the device’s requirement.
Release Date: February 1^st, 2016
13
– Revision B