W29N02GVSIAA Datasheet, PDF (11/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
4. PIN DESCRITPIONS
4.1 Chip Enable (#CE)
#CE pin enables and disables device operation. When #CE is high the device is disabled and the I/O
pins are set to high impedance and enters into standby mode if not busy. When #CE is set low the
device will be enabled, power consumption will increase to active levels and the device is ready for
Read and Write operations.
4.2 Write Enable (#WE)
#WE pin enables the device to control write operations to input pins of the device. Such as, command
instructions, addresses and data that are latched on the rising edge of #WE.
4.3 Read Enable (#RE)
#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the
I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented for
each #RE pulse.
4.4 Address Latch Enable (ALE)
ALE pin controls address input to the address register of the device. When ALE is active high,
addresses are latched via the I/O pins on the rising edge of #WE.
4.5 Command Latch Enable (CLE)
CLE pin controls command input to the command register of the device. When CLE is active high,
commands are latched into the command register via I/O pins on the rising edge of #WE.
4.6 Write Protect (#WP)
#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is active
low, all program/erase operations are disabled.
4.7 Ready/Busy (RY/#BY)
RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is
processing either a program, erase or read operations. When it returns to high, those operations have
completed. RY/#BY pin is an open drain.
4.8 Input and Output (I/Ox)
I/Ox bi-directional pins are used for the following; command, address and data operations.
Release Date: February 1^st, 2016
11
– Revision B