W29N02GVSIAA Datasheet, PDF (33/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9.2.3 RANDOM DATA INPUT (85h)
After the Page Program (80h) execution of the initial data has been loaded into the Cache Register,
if the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command
can perform this function to a new column address prior to the Program (10h) command. The
RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-14).
CLE
#CE
#WE
ALE
#RE
RY/#BY
I/Ox
80h
Address (5cycles)
Din
85h
(A2dcydcrleesss)
tPROG
Din
10h
70h
Status
Don’t care
Figure 9-13 Random Data Input
9.2.4 CACHE PROGRAM (80h-15h)
CACHE PROGEAM (80h) command is started by writing the command to the Command Register.
The next writes should be five cycles of address, and then either writing a full or partial page of input
data into the Cache Register. Issuing the CACHE PROGRAM (15h) command to the Command
Register, starting transferring data from the Cache Register to the Data Register on the rising edge
of #WE and RY/#BY will go LOW. Programming to the array starts after the data has been copied
into the Data Register and RY/#BY returns to HIGH.
When RY/#BY returns to HIGH, the next input data can be written to the Cache Register by issuing
another CACHE PROGRAM command series. The time RY/#BY goes LOW, is typical controlled by
the actual programming time. The time for the first programming pass equals the time it takes to
transfer the data from the Cache Register to the Data Register. On the second and subsequent
programming passes, data transfer from the Cache Register to the Data Register is held until Data
Register content is programming into the NAND array.
The CACHE PROGRAM command can cross block address boundaries. RANDOM DATA INPUT
(85h) commands are permitted with CACHE PROGRAM operations. Status Register’s Cache
RY/#BY (Bit 6 or I/O6) can be read after issuing the READ STATUS (70h) command for confirming
when the Cache Register is ready or busy. RY/#BY, always follows Status Register Bit 6 (I/O6). Status
Register’s RY/#BY Bit 5 (I/O5) can be polled to determine whether the array programming is in
progress or completed for the current programming cycle.
Release Date: February 1^st, 2016
33
– Revision B