W29N02GVSIAA Datasheet, PDF (19/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9.1.2.1. SEQUENTIAL CACHE READ (31h)
The SEQUENTIAL CACHE READ (31h) copies the next page of data in sequence within block to the
Data Register while the previous page of data in the Cache Register is available for output. This is
done by issuing the command (31h), RY/#BY signal goes LOW and the STATUS REGISTER bits 6
and 5 = “00” for the period of tRCBSY. When RY/#BY signal goes HIGH and STATUS REGISTER
bits 6 and 5 = “10”, data at the Cache Register is available. The data can be read out from the Cache
Register by toggling #RE, starting address is column 0 or by using the RANDOM DATA OUTPUT
command for random column address access.
CLE
#CE
#WE
ALE
#RE
I/Ox
RY/#BY
00h
Address(5cycles)
30h
31h
Data Output (Serial Access)
tR
tRCBSY
31h
tRCBSY
Data output (Serial Access)
Figure 9-2 Sequential Cache Read Operations
Don’t care
9.1.2.2. RANDOM CACHE READ (00h-31h)
The RANDOM CACHE READ (00h-31h) will copy a particular page from NAND array to the Data
Register while the previous page of data is available at the Cache Register output. Perform this
function by first issuing the 00h command to the Command Register, then writing the five address
cycles for the desired page of data to the Address Register. Then write the 31h command to the
Command Register. Note; the column address bits are ignored.
After the RANDOM CACHE READ command is issued, RY/#BY signal goes LOW and STATUS
REGISTER bits 6 and 5 equal “00” for the period of tRCBSY. When RY/#BY signal goes HIGH and
STATUS REGISTER bits 6 and 5 equal “10”, the page data in the Cache Register is available. The
data can read out from the Cache Register by toggling #RE, the starting column address will be 0 or
use the RANDOM DATA OUTPUT (05h-E0h) command change the column address to start reading
out the data.
Release Date: February 1^st, 2016
19
– Revision B