W29N02GVSIAA Datasheet, PDF (17/79 Pages) Winbond – W29N02GV 2G-BIT 3.3V NAND FLASH MEMORY

W29N02GV
9. DEVICE OPERATIONS
9.1 READ operation
9.1.1 PAGE READ (00h-30h)
When the device powers on, 00h command is latched to command register. Therefore, system only
issues five address cycles and 30h command for initial read from the device. This operation can also
be entered by writing 00h command to the command register, and then write five address cycles,
followed by writing 30h command. After writing 30h command, the data is transferred from NAND
array to Data Register during tR. Data transfer progress can be done by monitoring the status of the
RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is an alternate
method by using the READ STATUS (70h) command. If the READ STATUS command is issued
during read operation, the Read (00h) command must be re-issued to read out the data from Data
Register. When the data transfer is complete, RY/#BY signal goes HIGH, and the data can be read
from Data Register by toggling #RE. Read is sequential from initial column address to the end of the
page. (See Figure 9-1)
CLE
#CE
#WE
ALE
#RE
l/Ox
00h
RY/#BY
Address (5cycles)
30h
tR
Data Output ( Serial Access )
Figure 9-1 Page Read Operations
Don’t care
9.1.2 CACHE READ OPERATIONS
To obtain a higher degree of performance read operations, the device’s Cache and Data Register
can be used independent of each other. Data can be read out from the Cache Register, while array
data is transferred from the NAND Array to the Data Register.
The CACHE READ mode starts with issuing a PAGE READ command (00h-30h) to transfer a page
of data from NAND array to the Cache Register. RY/#BY signal will go LOW during data transfer
indicating a busy status. Copying the next page of data from the NAND array to the Data Register
while making the Cache Register page data available is done by issuing either a SEQUENTIAL
CACHE READ (31h) or RANDOM CACHE READ (00h-31h) command. The SEQUENTIAL CACHE
READ mode will copy the next page of data in sequence from the NAND array to the Data Register
or use the RANDOM CACHE READ mode (00h-31h) to copy a random page of data from NAND
array to the Data Register. The RY/#BY signal goes LOW for a period of tRCBSY during the page
data transfer from NAND array to the Data Register. When RY/#BY goes HIGH, this means that the
Release Date: February 1^st, 2016
17
– Revision B