LM3S5652 Datasheet, PDF (92/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

The Cortex-M3 Processor
2.6.3
2.6.4
2.7
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 92.
Table 2-12. Fault Status and Fault Address Registers
Handler
Status Register Name
Hard fault
Hard Fault Status (HFAULTSTAT)
Memory management Memory Management Fault Status
fault
(MFAULTSTAT)
Bus fault
Bus Fault Status (BFAULTSTAT)
Usage fault
Usage Fault Status (UFAULTSTAT)
Address Register Name
Register Description
-
page 149
Memory Management Fault page 143
Address (MMADDR)
page 150
Bus Fault Address
(FAULTADDR)
page 143
page 151
-
page 143
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
Power Management
The Cortex-M3 processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 132). For more information about the behavior of the sleep modes, see “System
Control” on page 184.
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November 17, 2011
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