LM3S5652 Datasheet, PDF (24/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Table of Contents
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 606
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 607
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 609
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 610
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 611
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 612
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 613
Controller Area Network (CAN) Module ..................................................................................... 614
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 635
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 637
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 639
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 640
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 641
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 642
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 644
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 645
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 645
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 646
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 646
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 648
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 648
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 649
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 649
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 650
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 650
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 651
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 651
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 653
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 653
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 655
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 655
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 655
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 655
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 655
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 655
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 655
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 655
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 656
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 656
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 657
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 657
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 658
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 658
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 659
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 659
Universal Serial Bus (USB) Controller ....................................................................................... 660
Register 1: USB Device Functional Address (USBFADDR), offset 0x000 ............................................ 679
Register 2: USB Power (USBPOWER), offset 0x001 ......................................................................... 680
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November 17, 2011
Texas Instruments-Production Data