LM3S5652 Datasheet, PDF (32/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Revision History
Table 1. Revision History (continued)
Date
April 2009
Revision Description
5368 ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 167).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Corrected bits 2:1 in I2CSIMR, I2CSRIS, I2CSMIS, and I2CSICR registers to be reserved bits
(cannot interrupt on start and stop conditions).
■ Corrected bits 15:11 in USBTXMAXP0/1/2 and USBRXMAXP0/1/2 registers to be reserved bits
(cannot define multiplier).
■ Additional minor data sheet clarifications and corrections.
January 2009
4724
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Added clarification as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Added section called "Setting the Device Address" for special considerations when writing the
USBFADDR register.
■ Corrected USBEPIDX to be an 8-bit register.
■ Added comparator operating mode tables.
■ Corrected pin types of signals RST to "in" and USB0RBIAS to "out".
■ Additional minor data sheet clarifications and corrections.
November 2008
4283
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
32
November 17, 2011
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