LM3S5652 Datasheet, PDF (493/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits
wide and contains information for one possible sample. See the ADCSSCTL0 register on page 484
for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TS0
IE0
END0
D0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Bit/Field
31:4
3
2
1
0
Name
reserved
TS0
IE0
END0
D0
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
R/W
1
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
November 17, 2011
493
Texas Instruments-Production Data