LM3S5652 Datasheet, PDF (5/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
6
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
Hibernation Module .............................................................................................. 241
Block Diagram ............................................................................................................ 242
Signal Description ....................................................................................................... 242
Functional Description ................................................................................................. 243
Register Access Timing ............................................................................................... 243
Clock Source .............................................................................................................. 243
Battery Management ................................................................................................... 245
Real-Time Clock .......................................................................................................... 245
Battery-Backed Memory .............................................................................................. 245
Power Control ............................................................................................................. 246
Initiating Hibernate ...................................................................................................... 246
Interrupts and Status ................................................................................................... 246
Initialization and Configuration ..................................................................................... 247
Initialization ................................................................................................................. 247
RTC Match Functionality (No Hibernation) .................................................................... 247
RTC Match/Wake-Up from Hibernation ......................................................................... 247
External Wake-Up from Hibernation .............................................................................. 248
RTC/External Wake-Up from Hibernation ...................................................................... 248
Register Map .............................................................................................................. 248
Register Descriptions .................................................................................................. 249
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
Internal Memory ................................................................................................... 263
Block Diagram ............................................................................................................ 263
Functional Description ................................................................................................. 263
SRAM Memory ............................................................................................................ 263
ROM Memory ............................................................................................................. 264
Flash Memory ............................................................................................................. 264
Flash Memory Initialization and Configuration ............................................................... 266
Flash Programming ..................................................................................................... 266
Nonvolatile Register Programming ............................................................................... 266
Register Map .............................................................................................................. 267
ROM Register Descriptions (System Control Offset) ...................................................... 268
Flash Register Descriptions (Flash Control Offset) ......................................................... 269
Flash Register Descriptions (System Control Offset) ...................................................... 277
8
Micro Direct Memory Access (μDMA) ................................................................ 292
8.1 Block Diagram ............................................................................................................ 293
8.2 Functional Description ................................................................................................. 293
8.2.1 Channel Assigments .................................................................................................... 294
8.2.2 Priority ........................................................................................................................ 294
8.2.3 Arbitration Size ............................................................................................................ 294
8.2.4 Request Types ............................................................................................................ 295
8.2.5 Channel Configuration ................................................................................................. 295
8.2.6 Transfer Modes ........................................................................................................... 297
8.2.7 Transfer Size and Increment ........................................................................................ 305
8.2.8 Peripheral Interface ..................................................................................................... 305
8.2.9 Software Request ........................................................................................................ 305
8.2.10 Interrupts and Errors .................................................................................................... 306
8.3 Initialization and Configuration ..................................................................................... 306
8.3.1 Module Initialization ..................................................................................................... 306
November 17, 2011
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