LM3S5652 Datasheet, PDF (33/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
Table 1. Revision History (continued)
Date
October 2008
Revision Description
4149 ■ Added note on clearing interrupts to the Interrupts chapter:
Note:
It may take several processor cycles after a write to clear an interrupt source in order for
NVIC to see the interrupt source de-assert. This means if the interrupt clear is done as
the last action in an interrupt handler, it is possible for the interrupt handler to complete
while NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This can be avoided by either clearing the interrupt source at the
beginning of the interrupt handler or by performing a read or write after the write to clear
the interrupt source (and flush the write buffer)
■ Added clarification on JTAG reset to the JTAG chapter:
In order to reset the JTAG module after the device has been powered on, the TMS input must be
held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains.
■ The binary value was incorrect in the JTAG 16-bit switch sequence in the JTAG-to-SWD Switching
section in the JTAG chapter. Sentence changed to:
The 16-bit switch sequence for switching to JTAG mode is defined as b1110011100111100,
transmitted LSB first.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ Step 1 of the Initialization and Configuration procedure in the ADC chapter states the wrong register
to use to enable the ADC clock. Sentence changed to:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register.
■ In the CAN chapter, major improvements were made including a rewrite of the conceptual information
and the addition of new figures to clarify how to use the Controller Area Network (CAN) module.
■ In the USB chapter, clarified endpoint terminology and added a new section on DMA Operation.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
■ Additional minor data sheet clarifications and corrections were made.
June 2008
2972 Started tracking revision history.
November 17, 2011
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