LM3S5652 Datasheet, PDF (715/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
OTG B / Device Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
SETENDC RXRDYC STALL SETEND DATAEND STALLED TXRDY RXRDY
Type W1C
W1C
W1C
RO
W1C
R/W
R/W
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
4
3
Name
SETENDC
RXRDYC
STALL
SETEND
DATAEND
Type
W1C
W1C
W1C
RO
W1C
Reset
0
0
0
0
0
Description
Setup End Clear
Writing a 1 to this bit clears the SETEND bit.
RXRDY Clear
Writing a 1 to this bit clears the RXRDY bit.
Send Stall
Value Description
0 No effect.
1 Terminates the current transaction and transmits the STALL
handshake.
This bit is cleared automatically after the STALL handshake is
transmitted.
Setup End
Value Description
0 A control transaction has not ended or ended after the DATAEND
bit was set.
1 A control transaction has ended before the DATAEND bit has
been set. The EP0 bit in the USBTXIS register is also set in this
situation.
This bit is cleared by writing a 1 to the SETENDC bit.
Data End
Value Description
0 No effect.
1 Set this bit in the following situations:
■ When setting TXRDY for the last data packet
■ When clearing RXRDY after unloading the last data
packet
■ When setting TXRDY for a zero-length data packet
This bit is cleared automatically.
November 17, 2011
715
Texas Instruments-Production Data