LM3S5652 Datasheet, PDF (21/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
Register 16:
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Register 33:
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 381
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 382
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 383
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 385
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 386
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 388
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 389
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 390
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 391
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 392
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 393
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 394
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 395
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 396
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 397
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 398
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 399
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 400
General-Purpose Timers ............................................................................................................. 401
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 413
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 414
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 416
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 418
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 421
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 423
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 424
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 425
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 427
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 428
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 429
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 430
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 431
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 432
Register 15: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 433
Register 16: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 434
Watchdog Timer ........................................................................................................................... 435
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 439
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 440
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 441
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 442
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 443
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 444
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 445
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 446
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 447
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 448
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 449
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 450
November 17, 2011
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