LM3S5652 Datasheet, PDF (263/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
7 Internal Memory
The LM3S5652 microcontroller comes with 32 KB of bit-banded SRAM and 128 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1 Block Diagram
Figure 7-1 on page 263 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 7-1. Flash Block Diagram
ROM Control
RMCTL
ROM Array
Cortex-M3
Icode Bus
Dcode Bus
Flash Control
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
Flash Array
7.2
7.2.1
Bridge
Flash Protection
FMPREn
FMPPEn
SRAM Array
Flash Timing
USECRL
User Registers
USER_DBG
USER_REG0
USER_REG1
USER_REG2
USER_REG3
Functional Description
This section describes the functionality of the SRAM, ROM, and Flash memories.
SRAM Memory
Note:
The SRAM memory is implemented using two 32-bit wide SRAM banks (separate SRAM
arrays). The banks are partitioned so that one bank contains all even words (the even bank)
and the other contains all odd words (the odd bank). A write access that is followed
immediately by a read access to the same bank will incur a stall of a single clock cycle.
However, a write to one bank followed by a read of the other bank can occur in successive
clock cycles without incurring any delay.
November 17, 2011
263
Texas Instruments-Production Data