LM3S5652 Datasheet, PDF (14/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Revision History .................................................................................................. 28
Documentation Conventions ................................................................................ 35
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 60
Processor Register Map ....................................................................................... 61
PSR Register Combinations ................................................................................. 66
Memory Map ....................................................................................................... 74
Memory Access Behavior ..................................................................................... 76
SRAM Memory Bit-Banding Regions .................................................................... 79
Peripheral Memory Bit-Banding Regions ............................................................... 79
Exception Types .................................................................................................. 84
Interrupts ............................................................................................................ 85
Exception Return Behavior ................................................................................... 90
Faults ................................................................................................................. 91
Fault Status and Fault Address Registers .............................................................. 92
Cortex-M3 Instruction Summary ........................................................................... 94
Core Peripheral Register Regions ......................................................................... 97
Memory Attributes Summary .............................................................................. 100
TEX, S, C, and B Bit Field Encoding ................................................................... 103
Cache Policy for Memory Attribute Encoding ....................................................... 104
AP Bit Field Encoding ........................................................................................ 104
Memory Region Attributes for Stellaris Microcontrollers ........................................ 104
Peripherals Register Map ................................................................................... 105
Interrupt Priority Levels ...................................................................................... 130
Example SIZE Field Values ................................................................................ 158
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 162
JTAG Port Pins Reset State ............................................................................... 163
JTAG Instruction Register Commands ................................................................. 169
System Control & Clocks Signals (64LQFP) ........................................................ 173
Reset Sources ................................................................................................... 174
Clock Source Options ........................................................................................ 179
Possible System Clock Frequencies Using the SYSDIV Field ............................... 181
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 181
System Control Register Map ............................................................................. 185
RCC2 Fields that Override RCC fields ................................................................. 203
Hibernate Signals (64LQFP) ............................................................................... 242
Hibernation Module Register Map ....................................................................... 248
Flash Protection Policy Combinations ................................................................. 265
User-Programmable Flash Memory Resident Registers ....................................... 267
Flash Register Map ............................................................................................ 267
DMA Channel Assignments ............................................................................... 294
Request Type Support ....................................................................................... 295
Control Structure Memory Map ........................................................................... 296
Channel Control Structure .................................................................................. 296
μDMA Read Example: 8-Bit Peripheral ................................................................ 305
μDMA Interrupt Assignments .............................................................................. 306
Channel Control Structure Offsets for Channel 30 ................................................ 307
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November 17, 2011
Texas Instruments-Production Data