LM3S5652 Datasheet, PDF (356/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

General-Purpose Input/Outputs (GPIOs)
Table 9-3. GPIO Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PE1
5
I/O
TTL
GPIO port E bit 1.
PE2
2
I/O
TTL
GPIO port E bit 2.
PE3
1
I/O
TTL
GPIO port E bit 3.
PE4
8
I/O
TTL
GPIO port E bit 4.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
9.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block(see Figure
9-1 on page 357 and Figure 9-2 on page 358). The LM3S5652 microcontroller contains five ports and
thus five of these physical GPIO blocks.
356
November 17, 2011
Texas Instruments-Production Data