LM3S5652 Datasheet, PDF (12/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Table of Contents
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 541
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 542
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 542
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 543
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 544
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 544
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 545
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 546
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 546
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 547
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 548
Figure 15-1. I²C Block Diagram ............................................................................................. 578
Figure 15-2. I²C Bus Configuration ........................................................................................ 579
Figure 15-3. START and STOP Conditions ............................................................................. 579
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 580
Figure 15-5. R/S Bit in First Byte ............................................................................................ 580
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 580
Figure 15-7. Master Single SEND .......................................................................................... 584
Figure 15-8. Master Single RECEIVE ..................................................................................... 585
Figure 15-9. Master Burst SEND ........................................................................................... 586
Figure 15-10. Master Burst RECEIVE ...................................................................................... 587
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 588
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 589
Figure 15-13. Slave Command Sequence ................................................................................ 590
Figure 16-1. CAN Controller Block Diagram ............................................................................ 615
Figure 16-2. CAN Data/Remote Frame .................................................................................. 616
Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 624
Figure 16-4. CAN Bit Time .................................................................................................... 628
Figure 17-1. USB Module Block Diagram ............................................................................... 661
Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 758
Figure 18-2. Structure of Comparator Unit .............................................................................. 759
Figure 18-3. Comparator Internal Reference Structure ............................................................ 760
Figure 19-1. 64-Pin LQFP Package Pin Diagram .................................................................... 770
Figure 22-1. Load Conditions ................................................................................................ 787
Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 790
Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 790
Figure 22-4. External Reset Timing (RST) .............................................................................. 791
Figure 22-5. Power-On Reset Timing ..................................................................................... 791
Figure 22-6. Brown-Out Reset Timing .................................................................................... 791
Figure 22-7. Software Reset Timing ....................................................................................... 791
Figure 22-8. Watchdog Reset Timing ..................................................................................... 792
Figure 22-9. Hibernation Module Timing ................................................................................. 793
Figure 22-10. ADC Input Equivalency Diagram ......................................................................... 794
Figure 22-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 795
Figure 22-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 795
Figure 22-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 796
Figure 22-14. I²C Timing ......................................................................................................... 797
12
November 17, 2011
Texas Instruments-Production Data