LM3S5652 Datasheet, PDF (701/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Stellaris® LM3S5652 Microcontroller
OTG A /
Host
OTG B /
Device
Register 19: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064
Register 20: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066
USBTXFIFOADD and USBRXFIFOADD are 16-bit registers that control the start address of the
selected transmit and receive endpoint FIFOs.
USB Transmit FIFO Start Address (USBTXFIFOADD)
Base 0x4005.0000
Offset 0x064
Type R/W, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ADDR
Type RO
RO
RO
RO
RO
RO
RO R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
15:9
8:0
Name
reserved
ADDR
Type
RO
R/W
Reset
0x00
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit/Receive Start Address
Start address of the endpoint FIFO.
Value Start Address
0x0 0
0x1 8
0x2 16
0x3 24
0x4 32
0x5 40
0x6 48
0x7 56
0x8 64
... ...
0x1FF 4095
November 17, 2011
701
Texas Instruments-Production Data