LM3S5652 Datasheet, PDF (792/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

Electrical Characteristics
22.2.5
22.2.6
Figure 22-8. Watchdog Reset Timing
WDOG
Reset
(Internal)
R9
/Reset
(Internal)
Sleep Modes
Table 22-17. Sleep Modes AC Characteristics^a
Parameter No Parameter
Parameter Name
Min Nom
D1
t_{WAKE_S}
Time to wake from interrupt in sleep or
-
-
deep-sleep mode, not using the PLL
D2
t_{WAKE_PLL_S} Time to wake from interrupt in sleep or
-
-
deep-sleep mode when using the PLL
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
Max
7
T_READY
Unit
system clocks
ms
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 V_DC or powered down with the same external voltage
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.
Table 22-18. Hibernation Module AC Characteristics
Parameter
No
Parameter
Parameter Name
Min Nom Max
Unit
H1
t_{HIB_LOW}
Internal 32.768 KHz clock reference rising
-
200
-
μs
edge to /HIB asserted
H2
t_{HIB_HIGH}
Internal 32.768 KHz clock reference rising
-
30
-
μs
edge to /HIB deasserted
H3
t_{WAKE_ASSERT} /WAKE assertion time
62
-
-
μs
H4
t_WAKETOHIB
/WAKE assert to /HIB desassert
H5
t_{XOSC_SETTLE}
XOSC settling time^a
62
-
124
μs
20
-
-
ms
H6
t_{HIB_REG_ACCESS} Access time to or from a non-volatile register 92
-
-
μs
in HIB module to complete
H7
t_{HIB_TO_VDD}
HIB deassert to VDD and VDD25 at minimum
-
-
250
μs
operational level
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
792
November 17, 2011
Texas Instruments-Production Data