LM3S5652 Datasheet, PDF (176/848 Pages) Texas Instruments – Stellaris® LM3S5652 Microcontroller

System Control
Figure 5-3. Reset Circuit Controlled by Switch
VDD
Stellaris®
R_PU
RST
R_S
C₁
5.2.2.4
5.2.2.5
Typical R_PU = 10 kΩ
Typical R_S = 470 Ω
C₁ = 10 nF
The R_PU and C₁ components define the power-on delay.
The external reset timing is shown in Figure 22-4 on page 791.
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (V_DD) drops
below a brown-out threshold voltage (V_BTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivalent to an assertion of the external RST input and the reset is held
active until the proper V_DD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 22-6 on page 791.
Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 184). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
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November 17, 2011
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