TLK3104SA_09 Datasheet, PDF (9/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
transmission latency (continued)
TXxP
TXxN
TDx[0−7]
td(T_Latency)
Byte to be Transmitted
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
10 Bit Code Transmitted
TCx
Figure 5. Transmitter Latency
channel clock to serial transmit clock synchronization
The TLK3104SA requires an external differential reference clock, RFCP/N, for the on-chip phase lock loop
(PLL) and the clock/data recovery loop. To compensate for arbitrary clock phase tolerance differences between
the reference clock and the data aligned to the transmit clock, a small FIFO in the parallel transmit data path
on each channel is employed. This FIFO has a depth of four bytes.
The reference clock and the transmit data clock(s) are assumed to be from a common source and only phase
misaligned due to different path delays as shown in Figures 6 and 7. The reference clock is multiplied in
frequency 10x to produce the internal serialization clock. The internal serialization clock is used to clock out the
serial transmit data.
Protocol Device
Channel
Logic
Channel A
TCA
TX
FIFO
TLK3104SA
Data A
Serdes
Core
Channel
Logic
Channel B
TX
FIFO
Data B
Serdes
Core
Channel
Logic
Channel C
TX
FIFO
Data C
Serdes
Core
Channel
Logic
Channel D
TX
FIFO
Data D
Serdes
Core
RFCP/RFCN
Xtal OSC
Figure 6. Transmit and Reference Clock Relationship (Channel Sync Mode)
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9